library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity acumulador is
   port(
      La_neg, Ea, CLK: in std_logic; -- neg significa negado (risco em cima)
      entrada_bw     : in std_logic_vector(7 downto 0);
   	saida_bw       : out std_logic_vector(7 downto 0):="ZZZZZZZZ"; -- saida para o barramento w
      saida_A       : out std_logic_vector(7 downto 0):="00000000" -- saida para o somador/subtrator
	);
end acumulador;

architecture arquitetura of acumulador is
	signal tmp_A : std_logic_vector(7 downto 0):="00000000";
	begin
	
    	process (CLK, La_neg)
     	begin
     		if (CLK'event and CLK='1') then
	         if(La_neg='0') then
   	      	tmp_A<=entrada_bw;
   	         saida_A<=tmp_A;
   	      end if;
   	   end if;
      end process;
         
      process (Ea,tmp_A)
      begin
      	if	(Ea'event or tmp_A'event) then
	         if(Ea='1') then
   	   	   saida_bw<=tmp_A;
   	      else
   	         saida_bw<="ZZZZZZZZ";
   	      end if;
   	   end if;
      end process;
      
end arquitetura; 
                    
                
